SDK axi_timer_ds764

Gernerate mode

 

  -       The value loaded into the load register and it is called the generate value.

 -       Load bit is in the TCSR(Timer Control Status Register)

o   1 : load the counter

  -       ARHT(Auto Reload/Hold)

o   1 : roll over all ‘1’s to all ‘0’

  -       GENT(Generate_out)

o   1 : output pulse is generated

 

Capture mode

 

  -       The value of the counter is stored in the load register

-         TINT bit set

  -       Counter up or down is dependent on the UDT bit

-         The capture signal is sampled within the Timer/Counter with the S_AXI_ACLK

-         Capture event is defined as the transition on the sampled to the asserted state

-         ARHT bit

o   0 : capture event occurs

o   If the load register is  not read, subsequence capture events do not update the load register and are lost

o   1 : In contrast with the ‘0’, overwriting

  -       UDT : Count  up or down

 

Pulse Width Modulation mode

 

-         Control frequency and duty factor

-         Timer0 : period ; Timer1 : high time for the PWM0 output

-         MDT bit in the TCSR set to ‘0’

-         PWMA0 bit & PWMB0 bit in TCSR1 must be set to ‘1’

-         Both Generate_Out bit must be set

-         C_GEN0_ASSERT & C_GEN1_ASSERT must be set to ‘1’

  -       Period and Duty factor can be determined by the TLR0(Timer Load Register)&TLR1

o   When UDT=’0’

§  PWM_PERIOD = (MAX_COUNT–TLR0 + 2) * AXI_CLOCK_PERIOD

§  PWM_HIGH_TIME = (MAX_COUNT-TLR1+2) *AXI_CLOCK_PERIOD

o   When UDT=’1’

§  PWM_PERIOD = (TLR0+2)*AXI_CLOCK_PERIOD

§  PWM_HIGH_TIME=(TLR1+2)*AXI_CLOCK_PERIOD

 

 

 

 

Cascade mode

 

  -       Two timer/counter are cascaded to operate as a single 64-bit counter/timer

-         C_ONE_TIMER_ONLY should be set to’0’

-         C_COUNT_WIDTH should be set to ‘32’(width of each timer)

-         When UDP=’1’

o   TIMING_INTERVERVAL = (TLR + 4)*AXI_CLOCK_PERIOD

-         When UDP= ‘0’

o   TIMING_INTERVERVAL = (MAX_COUNT-TLR+4)*AXI_CLOCK_PERIOD

 

Interrupt

 

  -       TC interrupt signals can be signaled or disabled with the ENIT bit in the TCST

 

Register Data Types and Organization : Little endian!(Byte, Half word, Word)

 

 

Registers

 

-         TCSR0(Timer Control Status Register)

-         TLR0(Timer Load Register)

-         TCR0(Timer/Counter Register)

-         TLR1

  -       T CR1

 

TCSR0

 

  -       CASC

o   Enable cascade mode of timers

o   0 : Disable cascaded operation

o   1 : Enable cascaded operation

-         ENALL

o   Enable All Timers

o   0  : No effect on timers

o   1 : Enable all timers

-       PWMA0

o   Enable Pulse Width Modulation for Timer0

o   0 : disable

o   1 : enable

  -       T0int

o   Timer interrupt

o   0 : No interrupt has occurred

o   1 : Interrupt has occurred

o   Writing 1 : Clear T0INT(Clear to ‘0’)

-         ENT0

o   0 : Disable timer

o   1 : Enable timer

-         ENIT0

o   Enable Interrupt for timer0

o   0 : Disable interrupt

o   1 : Enable interrupt

  -       LOAD0

o   1 : Loads timer with value in TLR0

-          ARHT0

o   Auto Reload/Hold Timer0

o   0 : Hold counter or capture trigger

o   1 : Reload generate value or overwrite capture value

-         CAPT0

o   Enable External Capture Trigger

o   1 : Enable

  -       GENT0

o   Enable External generate signal timer

o   1 : Enable

-         UDT0

o   UP/DOWN Count timer0

-         MDT0

o   Timer0 Mode

o   0 : Timer mode is generate

o   1 : Timer mode is Capture


그렇다고.....ㅋ