SRAM timing diagram

메모리에서 가장 간단한 SRAM 부터 시작욥

 

SRAM 의 Timing diagram 은 아주 간단한 편이다.

Here, I will ignore the setup time for address and data.

 

For write, we should set up the address and data on the A , D. And then we should generate the writing pulse which is long enough for the write access time.

For read, we should disassert the writing operation (W) and we should assert reading operation. Once we assert read operation, the memory start to give some data. But until we give the right address that we want to access, memory would give garbage data. If we present the specific address that we want to access, valid data will be available at the output after a delay of the Write Access Time Also after we change the address, data bus maintain the data during Output hold time.